Operating Systems: Internals and Design Principles, 6/E William Stallings - Chapter 1: Computer System Overview

Processor

Two internal registers

Memory address resister (MAR)

Specifies the address for the next read or write

Memory buffer register (MBR)

Contains data written into memory or receives data read from memory

 

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Chapter 1 Computer System OverviewPatricia Roy Manatee Community College, Venice, FL ©2008, Prentice Hall Operating Systems: Internals and Design Principles, 6/E William StallingsOperating SystemExploits the hardware resources of one or more processorsProvides a set of services to system usersManages secondary memory and I/O devicesBasic ElementsProcessorTwo internal registersMemory address resister (MAR)Specifies the address for the next read or writeMemory buffer register (MBR)Contains data written into memory or receives data read from memoryBasic ElementsProcessorI/O address registerI/O buffer registerBasic ElementsMain MemoryVolatileReferred to as real memory or primary memoryBasic ElementsI/O ModulesSecondary Memory DevicesCommunications equipmentTerminalsSystem busCommunication among processors, main memory, and I/O modulesComputer Components: Top-Level ViewProcessor RegistersUser-visible registersEnable programmer to minimize main memory references by optimizing register useControl and status registersUsed by processor to control operating of the processorUsed by privileged OS routines to control the execution of programsUser-Visible RegistersMay be referenced by machine languageAvailable to all programs – application programs and system programsUser-Visible RegistersDataAddressIndex register: Adding an index to a base value to get the effective addressSegment pointer: When memory is divided into segments, memory is referenced by a segment and an offsetStack pointer: Points to top of stackControl and Status RegistersProgram counter (PC)Contains the address of an instruction to be fetchedInstruction register (IR)Contains the instruction most recently fetchedProgram status word (PSW)Contains status informationControl and Status RegistersCondition codes or flagsBits set by processor hardware as a result of operationsExamplePositive, negative, zero, or overflow resultInstruction ExecutionTwo stepsProcessor reads (fetches) instructions from memoryProcessor executes each instructionBasic Instruction CycleInstruction Fetch and ExecuteThe processor fetches the instruction from memoryProgram counter (PC) holds address of the instruction to be fetched nextPC is incremented after each fetchInstruction RegisterFetched instruction loaded into instruction registerCategoriesProcessor-memory, processor-I/O, data processing, controlCharacteristics of a Hypothetical MachineExample of Program ExecutionInterruptsInterrupt the normal sequencing of the processorMost I/O devices are slower than the processorProcessor must pause to wait for deviceClasses of InterruptsProgram Flow of ControlProgram Flow of ControlProgram Flow of ControlInterrupt StageProcessor checks for interruptsIf interruptSuspend execution of programExecute interrupt-handler routineTransfer of Control via InterruptsInstruction Cycle with InterruptsProgram Timing: Short I/O WaitProgram Timing: Long I/O WaitSimple Interrupt ProcessingChanges in Memory and Registers for an InterruptChanges in Memory and Registers for an InterruptSequential Interrupt ProcessingNested Interrupt ProcessingMultiprogrammingProcessor has more than one program to executeThe sequence in which programs are executed depend on their relative priority and whether they are waiting for I/OAfter an interrupt handler completes, control may not return to the program that was executing at the time of the interruptMemory HierarchyFaster access time, greater cost per bitGreater capacity, smaller cost per bitGreater capacity, slower access speedThe Memory HierarchyGoing Down the HierarchyDecreasing cost per bitIncreasing capacityIncreasing access timeDecreasing frequency of access to the memory by the processorSecondary MemoryAuxiliary memoryExternalNonvolatileUsed to store program and data filesCache MemoryProcessor speed faster than memory access speedExploit the principle of locality with a small fast memoryCache and Main MemoryCache PrinciplesContains copy of a portion of main memoryProcessor first checks cacheIf desired data item not found, relevant block of memory read into cacheBecause of locality of reference, it is likely that future memory references are in that blockCache/Main-Memory StructureCache Read OperationCache PrinciplesCache sizeEven small caches have significant impact on performanceBlock sizeThe unit of data exchanged between cache and main memoryLarger block size yields more hits until probability of using newly fetched data becomes less than the probability of reusing data that have to be moved out of cacheCache PrinciplesMapping functionDetermines which cache location the block will occupyReplacement algorithmChooses which block to replaceLeast-recently-used (LRU) algorithmCache PrinciplesWrite policyDictates when the memory write operation takes placeCan occur every time the block is updatedCan occur when the block is replacedMinimize write operationsLeave main memory in an obsolete stateProgrammed I/OI/O module performs the action, not the processorSets the appropriate bits in the I/O status registerNo interrupts occurProcessor checks status until operation is completeInterrupt-Driven I/OProcessor is interrupted when I/O module ready to exchange dataProcessor saves context of program executing and begins executing interrupt-handlerInterrupt-Driven I/ONo needless waitingConsumes a lot of processor time because every word read or written passes through the processorDirect Memory AccessTransfers a block of data directly to or from memoryAn interrupt is sent when the transfer is completeMore efficient

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